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Low-cost FPGA family offers multiprotocol 3.2-G SerDes

This article was posted on 02/25/2009 and scheduled for print publication in April 2009.

 Low-cost FPGA family offers multiprotocol 3.2-G SerDes

 65-nm devices are said to offer lowest power consumption available

The third-generation low-cost 65-nm LatticeECP3 FPGA family offers multiprotocol 3.2-G SerDes with XAUI jitter compliance, DDR3 memory interfaces, and DSP capabilities. The devices have 17-K to 149-K logic elements and are said to take 85% less static power and 50% less dynamic power than equivalent Virtex and Stratix parts,

The ICs have up to 320 18 x 18-bit multipliers, up to 7 Mbits of memory, and up to 16 SerDes channels that take only 90 mW/channel at 3.2 Gbits/s and include pre-emphasis and equalization. The chips are supported by the ispLEVER design tool suite.

They come in 256 to 1,156-ball BGA packages and have optional 128-bit AES decryption. (LatticeECP3-70, 67-K LUTs, from $35 ea/25,000 — versions available now and through the 3rd qtr.)

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